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Ajat E Hukkoo

from Cupertino, CA
Age ~58
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Also known as:
Ajat O Hukkoo, Ajat P Hukkoo, Ajat R Hukkoo, Alat Hukkoo, Atat Hukkoo, Ajat O
Phone and address:
11513 Seven Springs Ln, Cupertino, CA 95014
(408) 252-4849
Related to:
Ramesh K HukkooPriti Hukkoo, 58
Connected to:
Ankur P Hukmani, 48Marilyn J Hukriede, 65Jo A Hula, 77James P Hulak, 56Jean M Hulak, 64Clare M Hulama, 55David Huland, 40Debra L Huland, 54Debby D Hulberg, 67Kristen L Hulberg, 37

Ajat Hukkoo Phones & Addresses

  • 11513 Seven Springs Ln, Cupertino, CA 95014 (408) 252-4849
  • Monte Vista, CA
  • 411 Frances St, Sunnyvale, CA 94086
  • Austin, TX
  • Santa Clara, CA
  • 11513 Seven Springs Ln, Cupertino, CA 95014 (408) 646-4663

Work

Company: Broadcom Jan 1, 2011 Position: Director, engineering

Education

Degree: Master of Science, Masters School / High School: The University of Texas at Austin 1988 to 1990 Specialities: Computer Engineering

Skills

Asic • Soc • Verilog • Semiconductors • Eda • Ic • Rtl Design • Embedded Systems • Vlsi • Debugging • Low Power Design • Integrated Circuit Design • Rf • Processors • Functional Verification • Embedded Software • Physical Design • Digital Signal Processors • Tcl • Arm • Fpga • Microprocessors • Device Drivers • Timing Closure • Dft

Languages

Hindi

Emails

a***[email protected]

Industries

Semiconductors

Resumes

Resumes

Ajat Hukkoo Photo 1

Director, Engineering

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Location:
San Francisco, CA
Industry:
Semiconductors
Work:
Broadcom
Director, Engineering
Broadcom 2006 - 2009
Senior Manager, Ic Design Engineering
Broadcom 2004 - 2006
Senior Principal Engineer
Broadcom 2000 - 2004
Principal Engineer
Silicon Spice 1999 - 2000
Member of Technical Staff
Education:
The University of Texas at Austin 1988 - 1990
Master of Science, Masters, Computer Engineering Indian Institute of Technology, Bombay 1984 - 1988
Skills:
Asic
Soc
Verilog
Semiconductors
Eda
Ic
Rtl Design
Embedded Systems
Vlsi
Debugging
Low Power Design
Integrated Circuit Design
Rf
Processors
Functional Verification
Embedded Software
Physical Design
Digital Signal Processors
Tcl
Arm
Fpga
Microprocessors
Device Drivers
Timing Closure
Dft
Languages:
Hindi

Publications

Us Patents

Clock Signal Multiplication To Reduce Noise Coupled Onto A Transmission Communication Signal Of A Communications Device

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US Patent:
20130045779, Feb 21, 2013
Filed:
Sep 28, 2011
Appl. No.:
13/247295
Inventors:
Love KOTHARI - Sunnyvale CA, US
Ajat HUKKOO - Cupertino CA, US
Kerry Alan THOMPSON - Fort collins CO, US
Assignee:
Broadcom Corporation - Irvine CA
International Classification:
H04W 88/02
US Classification:
455572
Abstract:
A communications device is disclosed that implements a phase-locked-loop to multiply a clock signal provided to a power management unit (PMU) by a variable integer value. Multiplying the PMU clock signal provides a second clock signal where the second clock signal is characterized by a fundamental component with one or more harmonics of the fundamental component that differ from the fundamental component and the one or more harmonics of the PMU clock signal. The fundamental component with one or more harmonics of the second clock signal does not occupy the same communication channel as the transmission communication signal of the communications device. Thus, minimizing the degradation of the transmission communication signal.

Apparatus And Method To Combine Pin Functionality In An Integrated Circuit

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US Patent:
20130082764, Apr 4, 2013
Filed:
Sep 30, 2011
Appl. No.:
13/250677
Inventors:
Paul Penzes - Irvine CA, US
Love Kothari - Sunnyvale CA, US
Ajat Hukkoo - Cupertino CA, US
Mark Fullerton - Austin TX, US
Veronica Alarcon - San Jose CA, US
Zhongmin Zhang - Fremont CA, US
Kerry Alan Thompson - Fort Collins CO, US
Russell Radke - Fort Collins CO, US
Assignee:
BROADCOM CORPORATION - Irvine CA
International Classification:
G05F 3/02
H03B 1/00
G11C 5/14
US Classification:
327540, 327530, 327558
Abstract:
An apparatus and method are disclosed to combine pad functionality in an integrated circuit. A power, ground, or signal pad is connected to a power, ground, or signal source, respectively. The power, ground, or signal pad is additionally connected to an additional signal source, such as automatic test equipment in a testing environment. By temporarily disconnecting either the power, ground, or signal source, from the functional block within the integrated circuit to which the source is delivered, the same pad may pass in another signal to other portions of the integrated circuit. In the alternative, the same pad may pass in another signal to other portions of the integrated circuit without disconnecting the original signal by coupling the additional signal over the original signal. Further, combining pad functionality enables reuse of an input pad as an output pad for signals originating from within the integrated circuit.

Adaptive Ultra-Low Voltage Memory

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US Patent:
20130117626, May 9, 2013
Filed:
Nov 4, 2011
Appl. No.:
13/289691
Inventors:
Paul PENZES - Irvine CA, US
Mark Fullerton - Austin TX, US
Ajat Hukkoo - Cupertino CA, US
John Walley - Ladera Ranch CA, US
Assignee:
Broadcom Corporation - Irvine CA
International Classification:
H03M 13/09
G06F 11/10
G06F 1/26
US Classification:
714758, 713300, 714E11044
Abstract:
Embodiments provide an adaptive memory that allows for low voltage modes of operation. In the low voltage modes of operation, the supply voltage provided to the memory is reduced below Vcc(min), which allows for significant savings in the power consumption of circuit components (e.g., the CPU) whose minimum voltage is dictated by Vcc(min). According to further embodiments, the memory can be configured dynamically according to various configurations depending on desired power savings (e.g., target Vcc(min)) and/or performance requirements (e.g., reliability, cache size requirement, etc.).

Method And System For Data Packer Unit For Accelerating Stack Functions

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US Patent:
20070189232, Aug 16, 2007
Filed:
Feb 14, 2006
Appl. No.:
11/353889
Inventors:
Li Chang - Holmdel NJ, US
Ajat Hukkoo - Cupertino CA, US
International Classification:
H04B 7/216
US Classification:
370335000
Abstract:
Methods and systems for data packer unit for accelerating stack functions may include packing payload bits for HSDPA packets in sequence, in hardware, for example, a multistage pipeline, to form a data packet. The data packet may be aligned to start on a n-bit boundary, regardless of a bit position of the start of one or more of the payloads. The value of n may be a multiple of 8, such as, for example, 32. Bits, which may be zeros, for example, may be inserted to end of the data packet to pad the data packet to an n-bit boundary. The HSDPA packets may be fetched from memory, for example, by using variable burst DMA. The information to fetch the HSDPA packets may be stored, for example, in a linked list. The operation of packing the payloads from the fetched HSDPA packets may be controlled via a state machine.

Induction-Coupled Clock Distribution For An Integrated Circuit

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US Patent:
20160109899, Apr 21, 2016
Filed:
Oct 9, 2015
Appl. No.:
14/879905
Inventors:
- Irvine CA, US
Ajat HUKKOO - Cupertino CA, US
Assignee:
Broadcom Corporation - Irvine CA
International Classification:
G06F 1/10
Abstract:
An integrated circuit package including an induction-coupled clock distribution system is disclosed. An exemplary embodiment of the disclosure includes a transmission module coupled to a main clock line, a clock reception module coupled to the transmission module, the clock reception module including a clock output line, and an electronic circuit coupled to the clock output line of the clock reception module, the electronic circuit including at least one clocked element and configured to operate synchronously with a clocking signal received through the clock output line of the clock reception module. The transmission module may be disposed on the supporting case of the IC package, and the electronic circuit and the clock reception module may be disposed on the semiconductor die of the IC package.

Resonant Inductor Coupling Clock Distribution

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US Patent:
20150162914, Jun 11, 2015
Filed:
Feb 19, 2015
Appl. No.:
14/626445
Inventors:
- Irvine CA, US
Ajat HUKKOO - Cupertino CA, US
Assignee:
Broadcom Corporation - Irvine CA
International Classification:
H03K 19/096
H02J 5/00
H01F 38/14
Abstract:
The present disclosure provides for a clock distribution network for distributing clocking signals within a synchronous sequential logic circuit. The clock distribution network distributes the one or more clock signals by inductively and/or capacitively coupling a clocking signal from a primary distribution node to various secondary distribution nodes within the synchronous sequential logic circuit. The various secondary distribution nodes resonate at respective resonant frequencies to generate other clocking signals for use within the synchronous sequential logic circuit in response to receiving the clocking signal.

Resonant Inductor Coupling Clock Distribution

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US Patent:
20140210518, Jul 31, 2014
Filed:
Mar 22, 2013
Appl. No.:
13/849115
Inventors:
Broadcom Corporation - , US
Ajat HUKKOO - Cupertino CA, US
Assignee:
Broadcom Corporation - Irvine CA
International Classification:
H03K 19/096
US Classification:
326 93, 307104
Abstract:
The present disclosure provides for a clock distribution network for distributing clocking signals within a synchronous sequential logic circuit. The clock distribution network distributes the one or more clock signals by inductively and/or capacitively coupling a clocking signal from a primary distribution node to various secondary distribution nodes within the synchronous sequential logic circuit. The various secondary distribution nodes resonate at respective resonant frequencies to generate other clocking signals for use within the synchronous sequential logic circuit in response to receiving the clocking signal.

Induction-Coupled Clock Distribution For An Integrated Circuit

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US Patent:
20140210527, Jul 31, 2014
Filed:
Sep 13, 2013
Appl. No.:
14/027079
Inventors:
- Irvine CA, US
Ajat HUKKOO - Cupertino CA, US
International Classification:
H03L 7/06
US Classification:
327156, 327141
Abstract:
An integrated circuit package including an induction-coupled clock distribution system is disclosed. An exemplary embodiment of the disclosure includes a transmission module coupled to a main clock line, a clock reception module coupled to the transmission module, the clock reception module including a clock output line, and an electronic circuit coupled to the clock output line of the clock reception module, the electronic circuit including at least one clocked element and configured to operate synchronously with a clocking signal received through the clock output line of the clock reception module. The transmission module may be disposed on the supporting case of the IC package, and the electronic circuit and the clock reception module may be disposed on the semiconductor die of the IC package.
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Ajat E Hukkoo from Cupertino, CA, age ~58 Get Report