Aiguo Lu

6470487, Oct 22, 2002

Apr 25, 2001

09/842350

Andrej A. Zolotykh - Moskovskaya Oblast, RU
Elyar E. Gasanov - Moscow, RU
Ivan Pavisic - San Jose CA
Aiguo Lu - Cupertino CA

LSI Logic Corporation - Milpitas CA

G06F 1750

716 18

A method for resynthesizing a design of an integrated circuit using a parallel processing mode. A single processing mode is entered by activating a main thread and locking a semaphore associated with the main thread. The design of the integrated circuit is resynthesized using the main thread. Tasks to be accomplished in the parallel processing mode are identified. The semaphore associated with the main thread is unlocked, and the operation of the single processing mode is ceased. Ordinal threads are activated by unlocking a semaphore associated with each ordinal thread. The tasks are processed in parallel by assigning the tasks to the ordinal threads and the main thread. Upon completion of one of the assigned tasks by one of the ordinal threads, it is determined whether an additional task remains to be assigned. In the case where the additional task remains, the additional task is assigned to the completed one of the ordinal threads. In the case where the additional task does not remain, the completed one of the ordinal threads is inactivated.

6487697, Nov 26, 2002

Mar 28, 2001

09/820059

Aiguo Lu - Cupertino CA
Ivan Pavisic - San Jose CA
Andrej A. Zolotykh - Moskovaskaya Oblast, RU

LSI Logic Corporation - Milpitas CA

G06F 1750

716 2, 716 9, 716 6

Methods and apparatus are disclosed for inserting buffers into the design of an integrated circuit with a high fanout net. If a net has a ramptime violation, all of the driven elements in the net are clustered in such a manner that the total load (capacitance) of the driver decreases. Clustering is based upon a two-dimensional partitioning approach together with three proposed heuristics (expand, shrink and merge), which iteratively partitions the placement regions of the net such that the number of buffers to be inserted and the level of inserted buffer tree are minimized. After clustering, one buffer is inserted for each cluster created in the clustering operation. Each of the inserted buffers drives its corresponding cluster. The buffers that are inserted will not have any ramptime violation, which ensures converge of the buffer insertion scheme. Therefore, each insertion of a level of buffers reduces the overall ramptime of the net.

6546541, Apr 8, 2003

Feb 20, 2001

09/789108

Dusan Petranovic - Cupertino CA
Ivan Pavisic - San Jose CA
Aiguo Lu - Cupertino CA

LSI Logic Corporation - Milpitas CA

G06F 1750

716 18, 716 2, 716 9, 716 10

A method and apparatus are provided for generating constraints for an integrated circuit logic re-synthesis algorithm. The method and apparatus receive a netlist of interconnected logic elements, which includes a plurality of nets, wherein each of the nets is coupled between a respective net driver logic element and at least one driven logic element. The method and apparatus also receive a maximum allowable input ramp time specification for the logic elements and an output ramp time specification for the net driver logic elements. A maximum interconnect capacitance constraint is then generated for each of the net driver logic elements based on the output ramp time specification for that net driver logic element and the maximum allowable input ramp time specification.

6550044, Apr 15, 2003

Jun 19, 2001

09/885589

Ivan Pavisic - San Jose CA
Aiguo Lu - Cupertino CA
Andrej A. Zolotykh - Moskovskaya Oblast, RU
Elyar E. Gasanov - Moscow, RU

LSI Logic Corporation - Milpitas CA

G06F 1750

716 6, 716 18

A method of synthesizing a clock tree for an integrated circuit design is disclosed that includes the steps of constructing an initial balanced clock tree for an integrated circuit design; calculating a clock arrival time for each clock driven cell in the initial clock tree; performing a timing analysis from the clock arrival time calculated for each clock driven cell; and performing a skew optimization concurrently with the timing analysis to correct timing violations discovered by the timing analysis.

6550045, Apr 15, 2003

Nov 20, 2001

09/991574

Aiguo Lu - Cupertino CA
Ivan Pavisic - San Jose CA
Andrej A. Zolotykj - Moskovskaya Oblast, RU
Elyar E. Gasanov - Moscow, RU

LSI Logic Corporation - Milpitas CA

G06F 1750

716 6, 716 1, 716 2, 716 4, 716 10

Clock delays are changed in a clock network of an ASIC. Global skew optimization is achieved by restructuring a clock domain to balance clock delays in the domain, and by equalizing clock delays of several domains of a group that have timing paths between them. Clock delays are equalized using buffer chains affecting all leaves of the respective domain, and an additional delay coefficient that equalizes clock delay. The clock insertion delays are changed for each group by restructuring the buffers in the group, based on both the data and clock logics to optimize the paths. Local skew optimization is achieved by restructuring the clock domain using a heuristic algorithm and re-ordering the buffers of the domain. A computer program enables a processor to carry out the processes.

6553551, Apr 22, 2003

Apr 25, 2001

09/841825

Andrej A. Zolotykh - Moskovskaya Oblast, RU
Elyar E. Gasanov - Moscow, RU
Ivan Pavisic - San Jose CA
Aiguo Lu - Cupertino CA

LSI Logic Corporation - Milpitas CA

G06F 1750

716 6

A method of computing timing delays of timing edges of a path of an integrated circuit design. According to the method, all pins within the path are identified, and all timing edges defined by the pins within the path are identified. All pins within the path that are a leading pin of one of the time edge in the path are also identified. For each given pin within the path, a tabulation is made of a number of pins that are upstream from the given pin along a contiguous series of the timing edges in the path. A computational rank is assigned to the given pin based upon the tabulated number for the given pin. The timing edges are ordered for computation based upon the computational rank of the leading pin of each timing edge in the path, to produce an ordered list of timing edges. The timing delays of the timing edges of the path are computed according to the ordered list of timing edges.

6557144, Apr 29, 2003

Dec 14, 2000

09/737239

Aiguo Lu - Cupertino CA
Ivan Pavisic - San Jose CA
Pedja Raspopovic - Cupertino CA

LSI Logic Corporation - Milpitas CA

G06F 1750

716 2, 716 4, 716 9, 716 10, 716 18

A computer program that improves a netlist of logic nodes and physical placement for an IC. The program (a) identifies critical nodes based on delay information calculated from the physical placement. Then the program (b) selects a set of critical nodes and optimally collapses their critical fan-ins and part of the non-critical fan-ins based on their Boolean relationship, which, includes at least one critical node. After that, the program (c) remaps the collapsed sub-netlist by covering its subject graph with an optimal pattern graph, and dynamically estimates and updates the fanout loads. The program returns to step (b) if the remapped sub-netlist is unacceptable, and returns to step (a) after updating the delay information and coordinates of newly mapped gates if the remapped sub-netlist is acceptable. The program exits at step (a) when no more critical nodes are identified at step (a).

6629304, Sep 30, 2003

Sep 19, 2001

09/955698

Elyar E. Gasanov - Moscow, RU
Andrej A. Zolotykh - Fryazino, RU
Aiguo Lu - Cupertino CA
Ivan Pavisic - San Jose CA

LSI Logic Corporation - Milpitas CA

G06F 945

716 10, 716 9, 716 11

Cell overlap is removed from rows during a cell placement procedure for an integrated circuit chip. The rows are partitioned into subrows so that cells in each subrow have a common characteristic vector. Cell overflow is removed from each of the subrows by moving a cell of an overflowed row or exchanging two cells, at least one of which is in the overflowed subrow. The half-cells of the dual height cells are moved to cell positions in a suitable pair of rows based on a calculated movement penalty. The movement is accomplished to align the half-cells and minimize the penalty. In preferred embodiments, the process is carried out by a computer under control of a computer program.