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Adebabay Mulat Bekele

from Scotts Valley, CA
Age ~52
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Also known as:
Adebabay M Bekele, Adebabay Living Bekele, Adebabay M Bekelf, Mulat Bekele Adebabay, Bekele Y
Related to:
Kaleab A Bekele, 42Gashaw M Bekele, 54Yeweinshet M Bekele, 65Fikeraddis B Mulat, 45Yohannes B Asfaw, 56Marie MulatBekele J Tebebe, 63Marie M Bekele, 63Girma M Bekele, 60Woseneneh M Bekele, 47Abay M Bekele, 57
Connected to:
Abrham T Bekele, 46Alem G Bekele, 41Alemayehu C Bekele, 51Birhanu K Bekele, 56Eden M Bekele, 47Elshadey Y Bekele, 41Emma Bekele, 27Ermiyas S Bekele, 37Firew D Bekele, 52Gizaw A Bekele, 52

Adebabay Bekele Phones & Addresses

  • Scotts Valley, CA
  • Rockford, AL
  • Las Vegas, NV
  • 502 Adeline Ave, San Jose, CA 95136 (408) 582-4239
  • 1324 Essex Way, San Jose, CA 95117 (408) 871-1967
  • 1889 Winding Creek Ct, San Jose, CA 95148
  • 422 E Campbell Ave, Campbell, CA 95008
  • Santa Clara, CA
  • Morgan Hill, CA
  • 1750 Stokes St APT 124, San Jose, CA 95126 (408) 289-1401

Business Records

Name / Title
Company / Classification
Phones & Addresses
Adebabay Bekele
M
Csa Investments LLC
1727 De Marietta Ave, San Jose, CA 95126
502 Adeline Ave, San Jose, CA 95136
Adebabay Bekele
Pacific Progress & Solutions, LLC
Import,Export & Comission Agent
1889 Winding Crk Ct, San Jose, CA 95148

Publications

Us Patents

Differential Clock Driver Circuit

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US Patent:
7061283, Jun 13, 2006
Filed:
Apr 30, 2004
Appl. No.:
10/836969
Inventors:
Atul V. Ghia - San Jose CA, US
Adebabay M. Bekele - San Jose CA, US
Assignee:
Xilinx, Inc. - San Jose CA
International Classification:
H03B 1/00
US Classification:
327108, 327 52
Abstract:
A system for driving a differential signal on a signal line and converting the differential signal from a rail-to-rail differential signal to a small signal differential signal is described. An exemplary embodiment of the circuit includes a first programmable differential driver circuit receiving a differential input; a programmable delay circuit receiving the differential input and coupled to a second programmable differential driver circuit; and a summation circuit coupled to the first and second differential driver circuits.

Programmable Logic Device Having An Embedded Differential Clock Tree

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US Patent:
7126406, Oct 24, 2006
Filed:
Apr 30, 2004
Appl. No.:
10/837009
Inventors:
Vasisht Mantra Vadi - San Jose CA, US
Steven P. Young - Boulder CO, US
Atul V. Ghia - San Jose CA, US
Adebabay M. Bekele - San Jose CA, US
Suresh M. Menon - Sunnyvale CA, US
Assignee:
Xilinx, Inc. - San Jose CA
International Classification:
G06F 1/04
H03K 3/00
US Classification:
327293, 327296, 327298
Abstract:
A clock distribution network having: a backbone clock signal line configured to provide a differential clock signal; multiple branches coupled to the backbone clock signal line for distributing the differential clock signal to multiple programmable function elements; a first leaf node coupled to a first branch, where the first leaf node is configured to provide the differential clock signal to a first programmable function element; and a second leaf node coupled to a second branch, where the second leaf node is configured to provide a single ended clock signal derived from the differential clock signal to a second programmable function element.

Differential Clock Tree In An Integrated Circuit

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US Patent:
7129765, Oct 31, 2006
Filed:
Apr 30, 2004
Appl. No.:
10/836722
Inventors:
Vasisht Mantra Vadi - San Jose CA, US
Steven P. Young - Boulder CO, US
Atul V. Ghia - San Jose CA, US
Adebabay M. Bekele - San Jose CA, US
Suresh M. Menon - Sunnyvale CA, US
Assignee:
Xilinx, Inc. - San Jose CA
International Classification:
G06F 1/04
H03K 3/00
US Classification:
327293, 327295, 327297
Abstract:
A clock distribution network having: a main trunk configured to provide a differential clock signal; a plurality of branches coupled to the main trunk for distributing the differential clock signal to a plurality of circuit elements on the integrated circuit; and a plurality of switches coupling the main trunk to the plurality of branches.

Differential Clocking Scheme In An Integrated Circuit Having Digital Multiplexers

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US Patent:
7142033, Nov 28, 2006
Filed:
Apr 30, 2004
Appl. No.:
10/837388
Inventors:
Atul V. Ghia - San Jose CA, US
Adebabay M. Bekele - San Jose CA, US
Assignee:
Xilinx, Inc. - San Jose CA
International Classification:
G06F 1/04
H03K 3/00
US Classification:
327293, 327296, 327298, 326 41
Abstract:
A system for distributing a small signal differential signal to a circuit element. The system includes: a first converter configured to convert a first small signal differential signal to a first two phase full CMOS differential signal for input into the differential multiplexer; and a programmable driver circuit configured to boost an output current of the programmable driver circuit at selected frequencies and to convert two phase full CMOS differential signal outputs of the differential multiplexer to a second small signal differential signal.

High Speed Configurable Transceiver Architecture

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US Patent:
7187709, Mar 6, 2007
Filed:
Mar 1, 2002
Appl. No.:
10/090250
Inventors:
Suresh M. Menon - Sunnyvale CA, US
Atul V. Ghia - San Jose CA, US
Warren E. Cory - Redwood City CA, US
Paul T. Sasaki - Sunnyvale CA, US
Philip M. Freidin - Sunnyvale CA, US
Santiago G. Asuncion - San Jose CA, US
Philip D. Costello - San Jose CA, US
Vasisht M. Vadi - Mountain View CA, US
Adebabay M. Bekele - San Jose CA, US
Hare K. Verma - Cupertino CA, US
Assignee:
Xilinx, Inc. - San Jose CA
International Classification:
H04B 1/38
H04L 5/16
US Classification:
375219, 375222, 341100, 326 38, 326 39, 326 41, 326 47
Abstract:
One or more configurable transceivers can be fabricated on an integrated circuit. The transceivers contain various components having options that can be configured by turning configuration memory cells on or off. The integrated circuit may also contain programmable fabric. Other components in the transceivers can have options that are controlled by the programmable fabric. The integrated circuit may also contain one or more processor cores. The processor core and the transceivers can be connected by a plurality of signal paths that pass through the programmable fabric.

Differential Clock Tree In An Integrated Circuit

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US Patent:
7372299, May 13, 2008
Filed:
Aug 29, 2006
Appl. No.:
11/511779
Inventors:
Vasisht Mantra Vadi - San Jose CA, US
Steven P. Young - Boulder CO, US
Atul V. Ghia - San Jose CA, US
Adebabay M. Bekele - San Jose CA, US
Suresh M. Menon - Sunnyvale CA, US
Assignee:
Xilinx, Inc. - San Jose CA
International Classification:
H03K 19/177
US Classification:
326 41, 326 93, 326 38
Abstract:
A clock distribution network having: a main trunk configured to provide a differential clock signal; a plurality of branches coupled to the main trunk for distributing the differential clock signal to a plurality of circuit elements on the integrated circuit; and a plurality of switches coupling the main trunk to the plurality of branches.

Programmable Logic Device Having An Embedded Differential Clock Tree

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US Patent:
7414430, Aug 19, 2008
Filed:
Aug 29, 2006
Appl. No.:
11/511647
Inventors:
Vasisht Mantra Vadi - San Jose CA, US
Steven P. Young - Boulder CO, US
Atul V. Ghia - San Jose CA, US
Adebabay M. Bekele - San Jose CA, US
Suresh M. Menon - Sunnyvale CA, US
Assignee:
Xilinx, Inc. - San Jose CA
International Classification:
H03K 19/177
US Classification:
326 41, 326 93
Abstract:
A clock distribution network having: a backbone clock signal line configured to provide a differential clock signal; multiple branches coupled to the backbone clock signal line for distributing the differential clock signal to multiple programmable function elements; a first leaf node coupled to a first branch, where the first leaf node is configured to provide the differential clock signal to a first programmable function element; and a second leaf node coupled to a second branch, where the second leaf node is configured to provide a single ended clock signal derived from the differential clock signal to a second programmable function element.

Differential Clock Tree In An Integrated Circuit

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US Patent:
7518401, Apr 14, 2009
Filed:
Aug 29, 2006
Appl. No.:
11/511973
Inventors:
Vasisht Mantra Vadi - San Jose CA, US
Steven P. Young - Boulder CO, US
Atul V. Ghia - San Jose CA, US
Adebabay M. Bekele - San Jose CA, US
Suresh M. Menon - Sunnyvale CA, US
Assignee:
Xilinx, Inc. - San Jose CA
International Classification:
H01L 25/00
H03K 19/177
H03K 19/00
US Classification:
326 41, 326 93, 716 16
Abstract:
A clock distribution network having: a main trunk configured to provide a differential clock signal; a plurality of branches coupled to the main trunk for distributing the differential clock signal to a plurality of circuit elements on the integrated circuit; and a plurality of switches coupling the main trunk to the plurality of branches.
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Adebabay Mulat Bekele from Scotts Valley, CA, age ~52 Get Report