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Aaron Grenat Phones & Addresses

  • 100 Pagosa Ct, Austin, TX 78737 (512) 514-0256
  • 6302 Hillside Terrace Dr, Austin, TX 78749
  • West Lafayette, IN
  • Mountlake Ter, WA
  • Savannah, GA
  • Hays, TX
  • Wimberley, TX
  • 100 Pagosa Ct, Austin, TX 78737

Work

Company: Amd Feb 2013 Position: Fellow design engineer

Education

Degree: Bachelors, Bachelor of Science School / High School: Purdue University 1993 to 1998 Specialities: Electrical Engineering

Skills

Soc • Timing • Physical Design • Microprocessors • Debugging • Asic • Low Power Design • Logic Design • Verilog • Firmware • Vlsi • Processors • Static Timing Analysis • Analysis • Functional Verification • Rtl Design • Circuit Design • Simulations • Timing Closure • Eda • Drc • Primetime

Industries

Semiconductors

Resumes

Resumes

Aaron Grenat Photo 1

Fellow Design Engineer

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Location:
San Francisco, CA
Industry:
Semiconductors
Work:
Amd
Fellow Design Engineer

Amd
Principal Member of Technical Staff Design Engineer
Education:
Purdue University 1993 - 1998
Bachelors, Bachelor of Science, Electrical Engineering
Skills:
Soc
Timing
Physical Design
Microprocessors
Debugging
Asic
Low Power Design
Logic Design
Verilog
Firmware
Vlsi
Processors
Static Timing Analysis
Analysis
Functional Verification
Rtl Design
Circuit Design
Simulations
Timing Closure
Eda
Drc
Primetime

Publications

Us Patents

Clock Domain Crossing Buffer

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US Patent:
8584067, Nov 12, 2013
Filed:
Nov 2, 2010
Appl. No.:
12/938125
Inventors:
Michael J. Osborn - Hollis NH, US
Michael J. Tresidder - Newmarket, CA
Aaron J. Grenat - Austin TX, US
Joseph Kidd - Hudson MA, US
Priyank Parakh - Arlington MA, US
Steven J. Kommrusch - Fort Collins CO, US
Assignee:
Advanced Micro Devices, Inc. - Sunnyvale CA
International Classification:
G06F 17/50
G06F 9/455
US Classification:
716113, 716114, 716124, 716135, 716136, 703 13, 703 19
Abstract:
Techniques are disclosed relating to detecting and minimizing timing problems created by clock domain crossing (CDC) in integrated circuits. In various embodiments, one or more timing parameters are associated with a path that crosses between clock domains in an integrated circuit, where the one or more timing parameters specify a propagation delay for the path. In one embodiment, the timing parameters may be distributed to different design stages using a configuration file. In some embodiments, the one or more parameters may be used in conjunction with an RTL model to simulate propagation of a data signal along the path. In some embodiments, the one or more parameters may be used in conjunction with a netlist to create a physical design for the integrated circuit, where the physical design includes a representation of the path that has the specified propagation delay.

Method And Circuitry For Debugging A Power-Gated Circuit

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US Patent:
8595563, Nov 26, 2013
Filed:
Jul 18, 2011
Appl. No.:
13/184982
Inventors:
Benjamin Tsien - Fremont CA, US
Kiran Bondalapati - Los Altos CA, US
Hao Huang - Austin TX, US
William A. Hughes - San Jose CA, US
Eric Rentschler - Steamboat Springs CO, US
Jeremy Schreiber - Austin TX, US
Aaron J. Grenat - Austin TX, US
Assignee:
Advanced Micro Devices, Inc. - Sunnyvale CA
International Classification:
G06F 11/00
US Classification:
714 45, 714 35
Abstract:
Described are a circuit and a method of analyzing and correcting a fault occurring in operation of the circuit during a power gating sequence. The method includes executing a modification of the power gating sequence that includes maintaining operation of a trace capture buffer (TCB); recording, in the TCB, events occurring during the executing; and correcting the fault based on analysis of the events recorded in the TCB. The circuit includes a plurality of components including a TCB, and a switch configured to maintain power to the TCB in a first state and turn off power to the TCB in a second state.

Power-Gated Retention Flops

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US Patent:
20120131526, May 24, 2012
Filed:
Nov 22, 2010
Appl. No.:
12/951500
Inventors:
Jeremy P. Schreiber - Austin TX, US
Aaron Grenat - Austin TX, US
International Classification:
G06F 17/50
H03K 3/0233
US Classification:
716110, 327203
Abstract:
A power-gated retention flop circuit is disclosed. In one embodiment, a retention flop includes a first latch coupled to a first global voltage node and a virtual voltage node and configured to receive a data input signal, and a second latch coupled to receive the data input signal from the first latch, wherein the second latch is coupled to the first global voltage node and a second global voltage node. The second latch is configured to provide a data output signal based on the data input signal. A power-gating circuit is coupled between the virtual voltage node and the second global voltage node, wherein the power-gating circuit is configured to, when active, couple the virtual voltage node to the second global voltage node. Thus, the first latch may be powered down while the second latch remains powered on.

Propagation Simulation Buffer

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US Patent:
20140062555, Mar 6, 2014
Filed:
Nov 8, 2013
Appl. No.:
14/076020
Inventors:
Michael J. Tresidder - Newmarket, CA
Aaron J. Grenat - Austin TX, US
Joseph Kidd - Hudson MA, US
Priyank Parakh - Arlington MA, US
Steven J. Kommrusch - Fort Collins CO, US
Assignee:
Advanced Micro Devices, Inc. - Sunnyvale CA
International Classification:
H03K 5/153
G06F 17/50
US Classification:
327160, 716108
Abstract:
Techniques are disclosed relating to detecting and minimizing timing problems created by clock domain crossing (CDC) in integrated circuits. In various embodiments, one or more timing parameters are associated with a path that crosses between clock domains in an integrated circuit, where the one or more timing parameters specify a propagation delay for the path. In one embodiment, the timing parameters may be distributed to different design stages using a configuration file. In some embodiments, the one or more parameters may be used in conjunction with an RTL model to simulate propagation of a data signal along the path. In some embodiments, the one or more parameters may be used in conjunction with a netlist to create a physical design for the integrated circuit, where the physical design includes a representation of the path that has the specified propagation delay.

Platform Power Manager For Rack Level Power And Thermal Constraints

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US Patent:
20210349517, Nov 11, 2021
Filed:
Jul 21, 2021
Appl. No.:
17/381664
Inventors:
- Santa Clara CA, US
- Markham, CA
Larry David Hewitt - Austin TX, US
Kevin M. Lepak - Austin TX, US
Samuel D. Naffziger - Fort Collins CO, US
Adam Neil Calder Clark - Markham, CA
Aaron Joseph Grenat - Austin TX, US
Steven Frederick Liepe - Fort Collins CO, US
Sandhya Shyamasundar - Sunnyvale CA, US
Wonje Choi - Austin TX, US
Dana Glenn Lewis - Austin TX, US
Leonardo de Paula Rosa Piga - San Francisco CA, US
Assignee:
Advanced Micro Devices, Inc. - Santa Clara CA
ATI Technologies ULC - Markham
International Classification:
G06F 1/3225
G06F 1/3234
Abstract:
Platform power management includes boosting performance in a platform power boost mode or restricting performance to keep a power or temperature under a desired threshold in a platform power cap mode. Platform power management exploits the mutually exclusive nature of activities and the associated headroom created in a temperature and/or power budget of a server platform to boost performance of a particular component while also keeping temperature and/or power below a threshold or budget.

Platform Power Manager For Rack Level Power And Thermal Constraints

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US Patent:
20200379544, Dec 3, 2020
Filed:
May 31, 2019
Appl. No.:
16/428312
Inventors:
- Santa Clarla CA, US
- Markham, CA
Larry David Hewitt - Austin TX, US
Kevin M. Lepak - Austin TX, US
Samuel D. Naffziger - Fort Collins CO, US
Adam Neil Calder Clark - Markham, CA
Aaron Joseph Grenat - Austin TX, US
Steven Frederick Liepe - Fort Collins CO, US
Sandhya Shyamasundar - Austin TX, US
Wonje Choi - Austin TX, US
Dana Glenn Lewis - Austin TX, US
Leonardo de Paula Rosa Piga - Austin TX, US
Assignee:
Advanced Micro Devices, Inc. - Santa Clara CA
ATI Technologies ULC - Markham
International Classification:
G06F 1/3225
G06F 1/3234
Abstract:
Platform power management includes boosting performance in a platform power boost mode or restricting performance to keep a power or temperature under a desired threshold in a platform power cap mode. Platform power management exploits the mutually exclusive nature of activities and the associated headroom created in a temperature and/or power budget of a server platform to boost performance of a particular component while also keeping temperature and/or power below a threshold or budget.

Low Insertion Delay Clock Doubler And Integrated Circuit Clock Distribution System Using Same

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US Patent:
20150205323, Jul 23, 2015
Filed:
Jan 21, 2014
Appl. No.:
14/159967
Inventors:
- Sunnyvale CA, US
Arun Sundaresan Iyer - Bangalore, IN
Alok Baluni - Bangalore, IN
Aaron Grenat - Austin TX, US
Assignee:
Advanced Micro Devices, Inc. - Sunnyvale CA
International Classification:
G06F 1/04
H03K 3/012
H03L 7/08
H03K 19/20
Abstract:
A clock doubler includes a first NAND gate having a first input for receiving a clock input signal and a second input, a second NAND gate having a first input and a second input for receiving a complement of the clock input signal, an output NAND gate having a first and second inputs coupled to outputs of the first and second NAND gates, respectively, and an output for providing a clock output signal, an inverter chain having an input for receiving the clock input signal and responsive to first and second control signals to selectively provide a first true output to the first input of the second NAND gate, and a second complementary output to the second input of the first NAND gate, and a control signal generation circuit providing the first and second control signals in response to the outputs of the first and second NAND gates.
Aaron Joseph Grenat from Austin, TX, age ~49 Get Report